JLPEA MDPI

12/12/2025

👏 Highly Cited Paper in JLPEA!

📄 “Multi-Timescale Energy Consumption Management in Smart Buildings Using Hybrid Deep Artificial Neural Networks”
👤 Ibude, F.

This study introduces hybrid deep learning models—combining CNNs, LSTMs, BiLSTMs, and GRUs—to deliver highly accurate daily, hourly, and minute-by-minute energy consumption predictions in smart buildings. The proposed ensembles significantly outperform conventional neural network approaches, achieving an MSE of just 0.109 for minute-level forecasting. By capturing latent patterns more effectively than single-model architectures, these hybrid models offer a powerful foundation for demand-side management, enabling smarter energy use, reduced waste, and improved operational efficiency.

🔗 https://www.mdpi.com/2079-9268/14/4/54

11/12/2025

📣 Published in JLPEA!
📄 “A Dynamic Current Pulsing Technique to Improve the Noise Efficiency Factor of Neural Recording Amplifiers”
👤 Huo, Y. & Olsson III, R. H.

This work introduces a dynamic current pulsing technique combined with a specialized two-stage low-pass filter to significantly enhance the noise efficiency factor (NEF) in neural recording amplifiers. The design achieves an impressively low NEF of 1.55 at just 587.8 nW of power and 5.18 µV_rms integrated noise—surpassing performance achieved in static low- and high-current modes on the same chip. This approach offers a promising pathway for ultra-low-power implantable neural interfaces.

🔗 https://www.mdpi.com/2079-9268/15/4/67

10/12/2025

👏 Highly Cited Paper in JLPEA!
“Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower” by Jaime Ramírez-Angulo et al.

🔗 https://www.mdpi.com/2079-9268/13/2/28

📘 This influential and highly cited paper presents two advanced analog circuit designs based on the flipped voltage follower (FVF). The authors demonstrate a Class AB cascode FVF with dramatically enhanced slew rate and bandwidth, as well as a low-voltage current mirror offering exceptional gain accuracy, extremely low input resistance, and ultra-high output resistance. These innovations achieve outstanding figures of merit while maintaining modest power consumption, validated through post-layout simulations in 180 nm CMOS technology.

Stay tuned for more highlighted papers from our journal!

09/12/2025

📣 Published in JLPEA!
📄 “Research on the Security of SRAM-Based FPGAs in the Era of Artificial Intelligence”
👤 Zhou, J.

This review analyzes emerging security challenges for SRAM-based FPGAs as AI-driven architectures and application models introduce new threat vectors. It outlines a comprehensive taxonomy of FPGA security threats, evaluates current protection measures, highlights the evolving role of FPGA manufacturers in security, and identifies key research directions for safeguarding future FPGA systems.

🔗 https://www.mdpi.com/2079-9268/15/4/66

05/12/2025

👏 Highly Cited Paper!

📄 “Extreme Path Delay Estimation of Critical Paths in Within-Die Process Fluctuations Using Multi-Parameter Distributions”
👤 Runolinna, M. et al.

This study investigates the use of Pearson type IV and metalog distributions as alternatives to the normal distribution for modeling path delay in digital circuits. Results show that the six-term metalog distribution provides the best fit for simulated path delays, offering accurate confidence intervals for extreme quantiles and improved estimation of maximum clock frequency (FMAX) under within-die process fluctuations. The findings highlight significant differences between traditional normal-based estimates and multi-parameter approaches, particularly for large numbers of critical paths.

🔗 https://www.mdpi.com/2079-9268/13/1/22

Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distrib...

05/12/2025

📣 New paper published in JLPEA!

📄 “An Ultra‑Low‑Quiescent‑Current On‑Chip Energy Management Circuit in 65 nm CMOS for Energy Harvesting Applications”
👤 Shahabi, M. et al.

The authors present an ultra‑low‑power on‑chip energy management circuit — a key block in PMICs for energy‑harvesting systems — designed with a compact latch‑based core that avoids extra circuits (voltage references, comparators, logic), reducing area and power consumption. Fabricated in 65 nm CMOS, the circuit shows a quiescent current of just 170 nA at 3 V, with over 0.9 V voltage hysteresis, proving its robust performance under ultra‑low‑power conditions and suitability for energy‑harvesting applications. 🔋

🔗 https://www.mdpi.com/2079-9268/15/4/65

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suita...

04/12/2025

📣 Highly Viewed paper!

📄 “Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology”
👤 Siddiqui, M.F. et al.

This paper presents a low-power quadrature LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop frequency divider, designed for 2.4 GHz IoT and BLE receivers. The design achieves a wide tuning range (4.4–5.7 GHz), ultra-low power consumption (2.02 mW total), and excellent phase noise performance (−118.36 dBc/Hz), demonstrating energy-efficient high-performance operation in a compact 0.47 mm² chip area.

🔗 https://www.mdpi.com/2079-9268/13/4/54

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devic...