12/05/2025
Check out George Toms's feature in the December digital on "A Novel Synthesis Approach for Simplifying : Optimizing interconnects, fanouts and signal structures before ." https://digital.pcea.net/issues/december-2025/toms/
"As ( ) grow denser, faster and more power-constrained, designers face mounting challenges maintaining signal integrity, power efficiency and manufacturability. Traditionally, most optimization occurs after schematic capture – during placement and routing – when it’s often too late to remove structural inefficiencies.
A new logic-level approach directly impacts board-level performance and complexity. By optimizing interconnects, fanouts and signal structures before schematic capture, a new gate-level synthesis technology enables to start with a cleaner, more efficient foundation."
