IEEE Journal on Emerging and Selected Topics in Circuits and Systems

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⚙️ Check out this Highlight Paper from 2025 Q2: “GPTAC: Domain-Specific Generative Pre-Trained Model for Approximate Cir...
10/10/2025

⚙️ Check out this Highlight Paper from 2025 Q2: “GPTAC: Domain-Specific Generative Pre-Trained Model for Approximate Circuit Design Exploration”

✍️ Authored by: Weichuan Zuo, Hongyi Wu, Ruicheng Dai, Weikang Qian, and Jienan Chen

Designing fast, low-cost digital circuits is difficult due to their discrete nature and vast design space. This work introduces GPTAC, a domain-specific generative pre-trained model for automatic approximate circuit design. Using a specialized circuit language representation, GPTAC learns from gate-level code to generate circuits based on desired accuracy or area. A built-in check rule improves reliability, enabling GPTAC to produce approximate multipliers in under 15 seconds with 10–40% area reduction while using only 4GB of GPU memory.

🔗 Read the full paper on IEEE Xplore: https://loom.ly/Br6CM_0

📢 Special Issue Proposals – Deadline Soon!The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETC...
10/10/2025

📢 Special Issue Proposals – Deadline Soon!

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is inviting proposals for upcoming special issues (starting with the December 2026 issue and beyond).

We welcome interdisciplinary topics that address emerging challenges and opportunities in circuits and systems—bringing together thought leaders across academia and industry.

🔹 Assemble a team of 2–4 Guest Editors
🔹 Highlight innovative and impactful research themes
🔹 Submit proposals by October 20, 2025

👉 Access the full Call for Proposals here: https://loom.ly/Eaozs_k

Want to stay ahead in the rapidly evolving world of emerging technologies in circuits and systems? 🚀🤖 Make sure you're f...
10/08/2025

Want to stay ahead in the rapidly evolving world of emerging technologies in circuits and systems? 🚀🤖 Make sure you're following JETCAS on all of our social media accounts!

Whether you're a seasoned academic, a pioneering researcher, an innovative engineer, or simply curious about the next big thing in circuits, our channels are your go-to for the latest breakthroughs and essential insights in this exciting field.

Don't miss a beat! Stay connected:
🔹 Linkedin: https://loom.ly/l01xhVQ
🔹 Facebook: https://loom.ly/2YoNOe0

📑 Paper Highlight from IEEE JETCAS Q2 Issue - End-to-End Acceleration of Generative Models With Runtime Regularized KV C...
10/02/2025

📑 Paper Highlight from IEEE JETCAS Q2 Issue - End-to-End Acceleration of Generative Models With Runtime Regularized KV Cache Management

✍️ Authored By: Ashkan Moradifirouzabadi; Mingu Kang

Despite the remarkable success of generative language models, their expanding KV cache inflates memory-bandwidth demands during batch processing, creating major hurdles for hardware deployment. We counter this limitation with a hardware-algorithm co-design that embeds a Runtime Cache Eviction mechanism in the KV Memory Management Unit, continuously discarding the least relevant tokens based on the KV cache budget and replacing them with the newly generated ones. Our system compresses the KV cache by up to 8× and yields 1.52× energy savings with a 3.62× latency reduction.

🔗 Read the full article in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS): https://loom.ly/cIicuTo

🌟 Senior Editor Spotlight: Hiroo Sekiya 🌟We’re proud to highlight Hiroo Sekiya, Senior Editor for the IEEE Journal on Em...
10/01/2025

🌟 Senior Editor Spotlight: Hiroo Sekiya 🌟

We’re proud to highlight Hiroo Sekiya, Senior Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)!

Affiliated with Chiba University, Dr. Sekiya brings extensive expertise in circuits and systems, contributing to the advancement of emerging technologies in both research and practice.

Dr. Sekiya’s dedication to the IEEE CASS community helps foster innovation, collaboration, and excellence in circuits and systems research.

➿ Stay in the loop with the latest from the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS...
09/26/2025

➿ Stay in the loop with the latest from the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).

🔗 Visit this link and click "Add title to my alerts" on the upper right side of the page to sign up for alerts and never miss an issue👉 https://loom.ly/OR7LLxg

Check out this paper from JETCAS June 2025 Issue, "A Scalable and Energy-Efficient Processing-In-Memory Architecture for...
09/25/2025

Check out this paper from JETCAS June 2025 Issue, "A Scalable and Energy-Efficient Processing-In-Memory Architecture for Gen-AI."

✍️ Authored by: Gian Singh; Sarma Vrudhula

Executing LLMs poses significant computational and energy challenges on CPUs/GPUs, which incur high latency and energy consumption due to the Memory Wall. This work introduces CIDAN-3D, a unique Processing-in-Memory (PIM) architecture tailored for LLMs. It features an ultra-low-power Neuron Processing Element (NPE) with high compute density ( /Area), enabling efficient in-situ execution of LLM operations by leveraging high parallelism within DRAM. CIDAN-3D reduces data movement, improves locality, and achieves substantial gains in performance and energy efficiency-showing up to 3x throughput and 71x energy improvement for large decoder-only models compared to a prior near-memory design.

🔗 Read this paper on IEEE Xplore here: https://loom.ly/cJChjnU

💡JETCAS JUNE 2025 SPOTLIGHT PAPER💡"An Overview of Neural Rendering Accelerators: Challenges, Trends, and Future Directio...
09/23/2025

💡JETCAS JUNE 2025 SPOTLIGHT PAPER💡

"An Overview of Neural Rendering Accelerators: Challenges, Trends, and Future Directions."

✍️ Authored by: Junha Ryu; Hoi-Jun Yoo

Rapid advancements in neural rendering have revolutionized the fields of augmented reality (AR) and virtual reality (VR) by enabling photorealistic 3D modeling and rendering. However, deploying neural rendering on edge devices presents significant challenges due to computational complexity, memory inefficiencies, and energy constraints. This paper provides a comprehensive overview of neural rendering accelerators, identifying the major hardware inefficiencies across sampling, positional encoding, and multi-layer perception (MLP) stages. We explore hardware-software co-optimization techniques that address these challenges and provide a summary for in-depth analysis. Additionally, emerging trends like 3D Gaussian Splatting (3DGS) and hybrid rendering approaches are briefly introduced, highlighting their potential to improve rendering quality and efficiency. By presenting a unified analysis of challenges, solutions, and future directions, this work aims to guide the development of next-generation neural rendering accelerators, especially for resource-constrained environments

Read it on IEEE Xplore here: https://loom.ly/YMNXtWw

You don't want to miss "LightRot: A Light-weighted Rotation Scheme and Architecture for Accurate Low-bit Large Language ...
09/19/2025

You don't want to miss "LightRot: A Light-weighted Rotation Scheme and Architecture for Accurate Low-bit Large Language Model Inference," from the June 2025 issue of JETCAS.

✍️ Authored by: Sangjin Kim; Yuseon Choi; Jungjun Oh; Byeongcheol Kim; Hoi-Jun Yoo

Rotation-based quantization is one of the most effective LLM quantization schemes these days, but it incurs costly floating-point overhead and still leaves room for further optimization. LightRot introduces a lightweight and accurate rotation scheme by combining Grouped Local Rotation (GLR) and Outlier Direction Aligning (ODA) to reduce rotation costs and enhance quantizability. Fabricated in 28nm CMOS, the LightRot accelerator achieves 27.4 TOPS/W and state-of-the-art 4-bit inference accuracy on LLaMA2/3 models, validated by both perplexity and MT-Bench evaluations.

Read it here: https://loom.ly/D0XncZo

📢 Special Issue Proposals – Submit Today!The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCA...
09/18/2025

📢 Special Issue Proposals – Submit Today!

The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is inviting proposals for upcoming special issues (starting with the December 2026 issue and beyond).

We welcome interdisciplinary topics that address emerging challenges and opportunities in circuits and systems—bringing together thought leaders across academia and industry.

🔹 Assemble a team of 2–4 Guest Editors
🔹 Highlight innovative and impactful research themes
🔹 Submit proposals by October 20, 2025

👉 Access the full Call for Proposals here: https://loom.ly/Eaozs_k

Don't miss this June 2025 JETCAS paper, "A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softm...
09/17/2025

Don't miss this June 2025 JETCAS paper, "A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU."

✍️ Authored by: Andrea Belano; Yvan Tortorella; Angelo Garofalo; Luca Benini; Davide Rossi; Francesco Conti

There's a common misconception that "accelerating GEMM is enough" to support Transformers on edge SoCs. However, even with moderate GEMM acceleration, Transformer non-linearities can become a major bottleneck. This work introduces SoftEx, a novel hardware accelerator designed to efficiently compute these non-linearities. SoftEx significantly speeds up and reduces the energy consumption of Transformer computations, leading to substantial improvements in overall throughput and energy efficiency for AI inference.

🔗 Read it now: https://loom.ly/RZspVog

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