IEEE Journal on Emerging and Selected Topics in Circuits and Systems

09/01/2026

💻 Call for Papers: JETCAS invites submissions for the Special Issue on “Adaptive Reliability in Circuits and Systems for Exascale and Intelligent Computing Hardware.”

As exascale computing, AI, and intelligent edge-cloud infrastructures continue to advance, next-generation hardware must deliver not only greater performance and energy efficiency, but also adaptability and dependable operation. This Special Issue explores **adaptive reliability** as a foundational design principle for trustworthy, scalable, and resilient computing platforms.

Topics of interest include:
🔹 Adaptive and fault-tolerant circuits and architectures
🔹 Reliable AI and intelligent hardware accelerators
🔹 Self-healing and reconfigurable hardware
🔹 Reliability-aware VLSI and hardware/software co-design
🔹 In-memory, near-memory, and neuromorphic computing
🔹 Chiplet-based and heterogeneous integration
🔹 Thermal-, power-, and aging-aware circuit techniques
🔹 Secure and trustworthy adaptive hardware architectures
🔹 Emerging-device circuits for intelligent computing

Submission deadline: 1 November 2026

Learn more and view submission information: https://ieee-cas.org/publication/JETCAS

09/01/2026

The deadline to submit to the upcoming Special Issue, “Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography" has been extended! You now have until 1 October 2026 to submit your research.

Learn more and view the full Call for Papers: https://ieee-cas.org/publication/JETCAS

08/27/2026

Want to stay ahead in the rapidly evolving world of emerging technologies in circuits and systems? 🚀🤖 Make sure you're following JETCAS on all of our social media accounts!

Whether you're a seasoned academic, a pioneering researcher, an innovative engineer, or simply curious about the next big thing in circuits, our channels are your go-to for the latest breakthroughs and essential insights in this exciting field.

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08/26/2026

Don't miss the deadline to submit to the upcoming Special Issue, “Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography.”

As post-quantum cryptography (PQC) moves closer to widespread implementation, efficient and secure hardware acceleration is becoming increasingly important. This Special Issue welcomes research spanning PQC hardware acceleration, hardware-software co-design, benchmarking and performance optimization, side-channel security and countermeasures, lightweight architectures, reliability and robustness, design automation, AI-assisted design, and more.

Manuscript submissions are due 1 September 2026.

Learn more and view the full Call for Papers: https://ieee-cas.org/publication/JETCAS

08/19/2026

➿ Stay in the loop with the latest from the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).

🔗 Visit this link and click "Add title to my alerts" on the upper right side of the page to sign up for alerts and never miss an issue👉 https://loom.ly/OR7LLxg

Read the current issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems | IEEE Xplore

08/14/2026

🌟 Guest Editor Highlight for the Special Issue: Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography

Professor Máire O’Neill is Regius Professor in Electronics and Computer Engineering and Director of the Centre for Secure Information Technologies (CSIT) at Queens University Belfast, N.Ireland. She is also Director of the UK-wide Research Institute in Secure Hardware and Embedded Systems (RISE). Her research interests are hardware security and applied cryptography, more specifically, cryptographic hardware architecture design (including PQC and homomorphic encryption) side channel analysis, fault attacks, physical unclonable functions and hardware trojan detection. She previously held a UK EPSRC Leadership Fellowship (2008-2014), was a former holder of a UK Royal Academy of Engineering research fellowship (2003-2008) and led the €3.8M EU H2020 SAFEcrypto (Secure architectures for Future Emerging Cryptography) project (2014-2018), which focused on lattice-based PQC. She has previously served as Associate Editor for IEEE Transactions on Circuits and Systems I, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing, and has been a Guest Editor for several journals. She will serve on the Editorial Board of the CAS Magazine in 2026/2027. She is Past-Chair of the IEEE Circuits and Systems for Communications (CASCOM) Technical Committee. She is a Fellow of the Royal Academy of Engineering, a member of the Royal Irish Academy and Fellow of the Irish Academy of Engineering.

08/12/2026

🌟 Guest Editor Highlight for the Special Issue: Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography

Dr. Yuichi Hayashi is a Professor at the Nara Institute of Science and Technology (NAIST), Japan, where he leads the Information Security Engineering Laboratory. His research focuses on electromagnetic information security and hardware security, including side-channel analysis, intentional electromagnetic interference (IEMI)–induced leakage and faults, and countermeasures for embedded systems. Prof. Hayashi holds several leadership and committee positions within IEEE and related professional societies, including serving on the IEEE Electromagnetic Compatibility (EMC) Society Board of Governors (BoG) and as Subcommittee Chair for Electromagnetic Information Leakage in IEEE EMC Technical Committee 5, among others. As part of his recent professional activities, he has contributed to the organization of major IEEE conferences—serving as Organizing Committee Co-Chair of EMC Japan/APEMC Okinawa 2024 and as Technical Program Committee Chair of AsianHOST 2024. His research achievements have been recognized through the CHES 2014 Best Paper Award, the IEEE EMC Society Richard B. Schulz Best Transactions Paper Award (2024), the EMC Europe 2025 Best Paper Award, and other distinctions reflecting his sustained contributions to the field.

08/11/2026

🔍 Explore Past Issues of IEEE JETCAS!

Looking for cutting-edge research to inform your next project, strengthen your literature review, or find impactful work to cite? Dive into the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) archives!

📚 JETCAS features high-quality articles on emerging trends, novel methodologies, and interdisciplinary advances in circuits and systems — all published through IEEE Xplore.

By reading past issues, you can:
• Stay up to date on the latest research directions
• Find relevant studies to support your own work
• Incorporate trusted citations from a well-recognized journal
• Discover inspiration for your next submission or project

🔗 Read past issues:
https://ieeexplore.ieee.org/xpl/issues?punumber=5503868&isnumber=11313699

Expand your research horizons with insights from the JETCAS community! 📖✨

Browse all the issues of IEEE Journal on Emerging and Selected Topics in Circuits and Systems | IEEE Xplore

08/10/2026

🌟 Guest Editor Highlight for the Special Issue: Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography

Dr. Dur E Shahwar Kundi is currently a Cryptography Hardware Engineer at PQShield Ltd, London, U.K. She received her Ph.D. in Electrical Engineering with a specialization in Information Security from the National University of Sciences and Technology (NUST), Pakistan, in 2016. Her research interests include PQC hardware acceleration, efficient FPGA implementations of cryptographic primitives, and approximate computing for lightweight IoT devices. Dr. Kundi has a strong track record of academic and industrial research, with over 14 years of experience. She has made significant contributions to high-performance and resource-efficient hardware designs for PQC standards like CRYSTALS-Kyber (ML-KEM) and CRYSTALS-Dilithium (ML-DSA), including a patented NTT accelerator. She has served as a Technical Committee member for IEEE CASCOM and as a Session Chair for prestigious conferences including IEEE ISCAS. Her editorial experience includes reviewing for top-tier journals and conferences such as IEEE Transactions on Computers, IEEE Transactions on Circuits and Systems-I/II, Cryptographic Hardware and Embedded Systems (CHES) and the IEEE International Symposium on Circuits and Systems (ISCAS).

08/07/2026

🌟 Guest Editor Highlight for the Special Issue: Efficient and Secure Hardware Acceleration for Post-Quantum Cryptography

Corresponding Guest Editor (CGE): Dr. Jiafeng Xie is currently an Associate Professor at the Department of Electrical and Computer Engineering, Villanova University, Villanova, PA, USA. He received the Ph.D. from University of Pittsburgh in 2014. His research interests include PQC-oriented cryptographic engineering, hardware accelerator design, fully homomorphic encryption, fault detection & hardware security, and VLSI digital design. Dr. Xie has served as technical committee member for many reputed conferences such as DAC, ICCAD, HOST, CODES+ISSS, etc. He is currently serving as Associate Editor for IEEE T-SP and ACM TRETS. He is also serving as the Senior Associate Editor for IEEE TCAS-II. He received the IEEE Access Outstanding Associate Editor for the year of 2019, IEEE Philadelphia Section Engineer of the Year Award 2024, and the Best Paper Award from IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2019.